Embedded Processor Analysis/Simulation Tools

M. A. Harball
Tactical Electronic Warfare Division

N. Bond
CACI, Inc.

Introduction:The benefits of using embedded processors in larger systems are well documented- cheaper, faster processing, improved reliability, enhanced flexibility, etc. However, the embedded device also complicates development, analysis, testing, and validation. Functions developed in software create a new level of abstraction for system design and analysis. System operation with an embedded machine involves the interaction of the system hardware, the embedded processing hardware, and the embedded processing software. Validating the composite system requires demonstrating that all of these levels function and interact in real time as the designer intended. Our objective was to investigate and develop a flexible embedded system emulation/modeling architecture to provide the ability to rapidly and accurately model a number of standard, off-the-shelf embedded devices running in a user-defined simulated hardware environment. This facilitates rapid prototyping and simultaneous development of hardware and software.

Analysis of embedded systems software operation involves emulating or modeling the processor operation within the target system hardware. This is typically done using a commercial emulation package that provides the user with the ability to run or step through the program, examining and modifying processor and program registers and flags. This process provides accurate modeling and analysis of the interactions between the system hardware and software, but it also requires that the hardware be complete -the design and implementation finalized-to validate the entire system. Modeling fidelity is an important issue in this approach.

Our Approach: Our approach, developed under contract by CACI, Inc., replaces the target system hardware with a simulation contained in in-system programmable (ISP) field programmable gate arrays (FPGAs). An actual processor is substituted for the emulator stand-in. With both emulation logic and system logic functions provided within the FPGAs, the designer has the ability to monitor operation of the entire embedded system. The objective is an emulation environment that is flexible and able to support a variety of embedded machine designs. The first goal is to provide support capability for typical 8-bit and 16-bit microprocessors and 16- bit digital signal processor architectures. The embedded emulation logic design and interface is specific to each processor and in some cases to each model. However, once this interface is established, the logic analysis and code development tools are available from within the emulation/modeling tool set.

With a sample of the actual embedded machine running the code, modeling and validation issues are greatly simplified. Use of the processor as an emulator requires a set of hardware control tools to provide the usual emulation features and connect them to a host machine. These are coded into a second FPGA. This first design runs in a commercial off-theshelf (COTS) PC so that commercial FPGA development tools can be run on the same host. However, the ANSI-VITA-4 compatible industry package (IP) format allows the emulator hardware to be readily adapted to any host computer supported by a range of commercially available adaptor boards.

Figure 7 shows a diagram of our emulation architecture. All key hardware elements are contained in the IP card, which appears in Figs. 8 and 9 (top and bottom views). The processor itself is mounted on a separate card that plugs "piggy back" onto the IP card, so each processor requires its own processor adapter card (PAC) with the appropriate emulation control hardware configuration downloaded into the FPGA. Expanding to a second processor, e.g., adding a DSP chip for dedicated functions, is a matter of providing a second IP board, emulator control configuration, and PAC. A separate dedicated bus is available for direct connections between IP cards, providing the capability to mix and match processor configurations within a single host. The integrated package also provides a means to incorporate (via the FPGA) hardware-based logic analysis tools to monitor and modify the embedded code, the processor operation, and the modeled system hardware components-all in a very small physical package that can be installed in a desktop workstation such as a PC.

FIGURE 7
Embedded System Emulation Architecture.

Fig8 Image

FIGURE 8
IP memory and host interface hardware.

Fig9 Image

FIGURE 9
IP FPGA and processor interface hardware.

Conclusions: This approach has several important advantages. Since the system hardware model is loaded into an FPGA, it can be developed rapidly using standard commercial tools and modified easily as faults or improvements are identified. Software development and accurate, detailed functional analyses can be initiated with limited definition of the final system hardware. Finally, except for the core IP hardware and PAC cards, the entire system design (including the analysis tools and external hardware simulation) is user-definable via software and can be downloaded to the emulator at startup.

[Sponsored by ONR]