Modeling Single-Event Transients in Complex Digital Devices

Introduction: Requirements for onboard electronics of many satellites are greatly increasing. One approach to meeting these requirements is to use state-of-the-art commercial electronics. However, to ensure reliable on-orbit operation, effects of the natural space radiation environment must be considered. These effects can be divided into two categories: total dose and single-event transients. Total-dose radiation effects on electronics can result in a slow but steady shift of the threshold voltages of transistors. Eventually, the threshold voltage may have shifted so much that the transistor can no longer function. Characterization of total-dose tolerance is well understood. Single-event transient (SET) effects from radiation are typically the result of a single charged particle, such as a heavy ion, that strikes a sensitive region of a circuit and deposits energy, resulting in an unintended analog pulse. In a digital circuit, this pulse may cause a single-event upset (SEU), in which the logic value of a memory element is changed (i.e., a logic "1" becomes a logic "0" or vise versa). Characterization of single-event transient tolerance for simple digital devices, such as memories, is well understood. However, for a complex digital device, one that contains multiple functional modes and both combinational logic elements and memory elements, this is not the case. For this reason, a methodology to determine the effect of single-event transients in complex digital devices has been developed.

Methodology Development: The SET state-transition model, shown in Fig. 5, defines the framework of the methodology (Ref. 1, pp. 7-9). The model reduces the operation of the complex digital device into four separate fault states. State S1: No SETs or SEUs is the fault-free state; the device is operating correctly. From S1, an SET can occur on a logic gate. This will occur with transitional probability β2, causing a transition to S2: Logic Gate Transient. Also from S1, the SET can occur on a memory element with transitional probability β1, causing a transition to S3: SEU. From S2, if the logic gate transient is latched into a memory element, which occurs with transitional probability δ1, the state becomes S3: SEU. If the transient is not latched into a memory element and stops propagating, the state returns to S1, which occurs with transitional probability α2. From S3, if the SEU is overwritten before it can cause an error to the external system, the present state returns to S1. If, instead, the SEU causes an error to the external system, a transition to state S4: Failure occurs with transitional probability ε1.

Predicting the effect of single-event transients in a complex digital device involves determining the transitional probabilities in this model. The overall SET tolerance of the device is calculated by combining the transitional probabilities to account for all the possible paths from S1 to S4.

Methodology Validation: To validate this methodology, the SET tolerance of a candidate complex digital device was determined. This device was the KDLX microprocessor, a 16-bit version of the processor described in Ref. 2. Figure 6 shows the processor. It was fabricated using the MOSIS prototyping system on the Agilent (formerly Hewlett-Packard) 0.5 mm CMOS process.

Determining the transitional probabilities involves SET generation modeling, SET analog propagation modeling, clock-edge effects modeling, logic propagation modeling, and SEU propagation modeling. The purpose of SET generation modeling is to determine how an incident ion will generate a transient pulse that can be described electrically. It is accomplished using a dependent current source in SPICE (Simulation Program with Integrated Circuit Emphasis) to create a double exponential pulse. SET analog propagation is modeled using SPICE and determines whether or not this electrical transient pulse is amplified or attenuated as it propagates through the circuit. Clock-edge effects modeling determines the probability that an SET pulse will be latched into a memory element; it is also modeled in SPICE. Logic propagation is modeled by analysis and determines the probability that there is a clear logic path through which the transient can propagate. SEU propagation modeling determines the likelihood that an SEU will propagate to the output and cause a failure to the external system, or alternatively, the likelihood that the SEU will be overwritten and the state can return to the fault-free state, S1. SEU propagation is modeled using a combination of register-usage analysis and VHDL (Very high-speed integrated circuit Hardware Description Language) simulations.

FIGURE 6
Candidate complex digital device: the KDLX.

The results of the modeling were combined to predict the overall device cross-section of the KDLX processor for three different test programs. The overall device cross-section is a measure of the device's sensitivity to SETs. The true device cross-section was then measured by performing heavy-ion testing at the Radiation Effects Facility at the Texas A&M University Cyclotron Institute. Figure 7 compares the predicted and measured cross-sections. This comparison shows very good agreement between the predicted and measured cross-sections of the device for each of the three test programs (Ref. 1, p. 79). This validates the described methodology to determine the effects of single-event transients in a complex digital device.

Summary: A methodology to determine the effect of single-event transients on complex digital devices has been developed. The methodology is based on the SET state-transition model and was validated by performing radiation testing on a candidate device, the KDLX microprocessor. This validated methodology is important to the Navy and DOD because it enables the reliable use of state-of-the-art commercial electronics in spacecraft, resulting in enhanced performance while reducing size, weight, power, and cost of the spacecraft's electronics.

[Sponsored by ONR]