Fabrication of a Fast Turn-Off Transistor by Wafer Bonding
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K.D. Hobart and F.J. Kub
Electronics Science and Technology Division
A new power switching transistor is presently under development to meet Navy goals for future electric power requirements. These high speed or fast turn-off (FTO) power switching devices are extremely efficient and versatile. It is envisioned that many aspects of Navy propulsion, weaponry, and power distribution demands will be met with solid-state electronic components, thereby reducing the size and weight of the associated systems. The realization of the prototype devices has been made possible through a low-temperature wafer bonding process developed at NRL that allows arbitrary joining of functional power electronic device wafers. The result is a variety of high voltage structures with active device components on the top and bottom to control charge within the volume of the transistor. Specific examples of 3.3 kV FTOs show that energy loss incurred during power switching transients is significantly reduced.
The Navy's transformation to a fleet that is significantly more dependent on electric power as the primary means of providing energy for propulsion and weapons has placed significant emphasis on developing extremely efficient, high-voltage solid-state switching devices. Additionally, the increased magnitude of shipside electric power has generated new challenges in power distribution that are difficult to meet with conventional methods. A new class of electronic devices is presently under development to address the needs of the Navy's Advanced Electrical Power Systems program. One of the prime objectives of the program is to devise new power switching devices, dubbed Fast Turn-Off transistors or FTOs1-3 that have significantly lower energy loss and higher switching frequencies than conventional power switches. Faster power switching devices are desirable on Navy platforms for several reasons: First, as switching frequencies increase, the physical size and weight of passive components used in power conditioning systems are reduced. Secondly, the higher switching frequencies make it easier to filter harmonics, which improves both silent operation of Navy vessels and electrical power quality. Thirdly, the FTO is projected to reduce switching loss by a factor of 5-10 and thereby improve efficiency of power systems. The FTO concept is particularly relevant to very high voltage devices required to meet new system demands in which the shear volume of charge in the transistor becomes significant and faster switching becomes more difficult. The FTO will extend the useful voltage range of silicon power devices until a suitable replacement technology is qualified (e.g., silicon carbide-based electronics). To speed the development of FTOs, NRL has developed an advanced wafer bonding technology and has demonstrated a new double-side power switching device that shows dramatic improvement in performance over the state-of-the-art.4
Bipolar vs Unipolar Transistors
There are many types of power switching transistors, and each application draws on the best properties of a particular design. For high voltage applications, only devices from the family of "bipolar" type transistors can obtain sufficiently low voltage drop in the "on" state while also supporting high voltage in the "off" state. The low voltage drop in bipolar transistors is achieved by high levels of charge injection consisting of both electrons and holes into the thick portion of the device designed for high voltage stand-off. The bipolar device is compared to a unipolar transistor in which only one type of charge carrier (typically electrons) is responsible for conduction. Unipolar devices are not considered useful for high voltage because of their large voltage drop in the on state. The key challenge in any of these transistors is to remove the stored charge as quickly as possible and thus make the transition from the on to the off state efficiently. To achieve efficient switching, the current must cease immediately when the transistor is turned off. While this is the case in unipolar devices, it is typically not possible in bipolar devices because of the long transit time of charge carriers in the thick stand-off region of the device. The ideal power transistor would combine the low voltage drop of a high voltage bipolar device and the fast turn-off capabilities of a unipolar transistor.
The FTO closely approximates the ideal switch and improves on the fundamental trade-offs between blocking voltage, forward voltage drop, and switching loss. The key feature is the additional gate control on the bottom of the transistor to manipulate the injection of charge into the volume of the device. The top and bottom MOS (metal oxide semiconductor) gates (G1 and G2 in Fig. 1) together control the current flow through the external cathode and anode connections of the transistor (in this case E1 and E2, respectively, in Fig. 1). When a voltage is applied to the top gate G1, an electron channel is created that allows charge injection (of electrons) into the n-base region of the internal p-n-p transistor. This sets up a chain reaction in the p-n-p transistor, and holes are also injected into the base from the bottom emitter E2, which is forward biased (when wired as the anode). In this case, both electrons and holes are strongly injected into the base. This is described as "conductivity modulation" because the basic conductivity properties of the semiconductor are modified and the concentration of charge is 1000-10,000 times larger than when no charge is injected. With the base of the transistor in conductivity modulation, the total resistance across the device becomes extremely low. Consequently, the forward voltage drop decreases from around 500 V to approximately 3 V. Since the conductivity of unipolar devices cannot be modulated, their usefulness is limited to less than 1000 V for silicon and <3000 V for silicon carbide.
The disadvantage of conductivity modulation is that the large quantity of stored charge in the base requires relatively long times to remove. The transistor is turned off by removing the voltage signal to the top gate G1 (Fig. 2, green gate trace). This begins the turn-off process by extinguishing the electron channel and halting electron injection into the base. Because of their long lifetime and low mobility, holes exit much more slowly. This results in a current "tail" during the turn-off transient and is responsible for significant energy loss. Figure 2 shows how current and voltage across FTO affect the energy loss: anytime both voltage and current are simultaneously present across the transistor, power in the form of heat must be dissipated to the ambient. In the "on" state, there is always a small loss associated with the forward voltage drop of the transistor. In the "off" state, energy loss is negligible. During switching transients, the energy loss can be very high because of the finite time it takes to establish the high voltage (turn-off) or high current (turn-on). The higher the switching frequency, the larger the energy loss associated with the transient. Therefore, the switching frequency is fundamentally limited by how much energy loss, or heat, can be removed from the transistor. While significant advances in power switching transistor technology have been made in recent years, high voltage power transistors are presently limited to relatively low switching frequencies (tens of kHz).
The turn-off loss of a power transistor is controlled by the internal device physics. Much has been done in the recent past to improve the turn-off capability of high-voltage bipolar switching transistor such as IGBTs (insulating gate bipolar transistors). The internal physics still limits the carrier behavior. As the voltage rating of a transistor increases, the number of options becomes limited. For instance, the turn-off loss is improved by lifetime "killing" in which high-energy protons or electrons are implanted throughout the bulk of the transistor, creating slight lattice damage and carefully reducing the lifetime of electrons and holes. The downside of this approach is that the damage also produces undesirable leakage current and also increases the forward voltage drop. The second gate of the FTO allows the internal physics of the transistor to be manipulated to achieve very fast and efficient turn-off. The FTO improves the turn-off process by activating the bottom gate (G2) prior to turn-off (Fig. 2, orange gate trace). The effect is to reduce the injection of hole charge into the base and immediate extinction of hole injection once the transistor is switched off. As described below, the tail current is completely eliminated by the proper timing of G2, thereby implementing the performance of a unipolar device during transient operation.
Power Switching Circuits and Applications
IGBTs are the preferred device for high-voltage continuous power applications where the magnitude and phase of the power delivered to the load is controlled through pulse-width modulation (PWM). Such applications include motor controllers (e.g., for propulsion), voltage converters, and solid-state transformers. For pulse power applications such as pulsed weapons systems, various thyristor designs are favored for their high peak current and very fast turn-on rate ( dI/dt). Thyristors are current controlled devices. From this standpoint, they are less attractive than IGBTs, which are voltage controlled, thus simplifying the driver circuitry. The FTO is designed to be a more efficient replacement for IGBTs in motor controller and voltage converter circuits and is essentially a symmetrical, bidirectional IGBT (Fig. 1). The symmetric nature of the FTO and the ability to precisely control stored charge in the volume of the device allows the number of components in the basic PWM switching circuit element to be reduced. This is called a "half-bridge" or "phase leg" since it controls one of many phases necessary to energize the windings of large electric motors (Fig. 3). Simplifying the basic architecture to a circuit composed entirely of FTOs significantly impacts switching performance. The benefit comes in reduced switching energy loss.5 The ability to control stored charge in the volume of the device is the key advantage because excess stored charge is the primary cause of energy loss during a switching transient. Since the total loss increases as the device is cycled on and off, the switching frequency is limited by the amount of dissipated power that can be effectively removed from the transistor. Reducing energy loss and increasing switching frequency are the main goals of the FTO program because the size and weight of passive components associated with the power module decrease as the switching frequency increases (both the inductance L and the capacitance C scale inversely with frequency). With present technology, the shear size of passive components (inductors, capacitors, transformers) precludes the introduction of certain capabilities due to size and weight restrictions. This article describes the fabrication, operation, and performance of a high-voltage FTO and shows that switching losses are significantly reduced.
FTO Transistor Fabrication
Fabrication of the FTO depends on the unique low-temperature wafer bonding process developed at NRL, which allows the joining of fully functional device wafers. Significant research was performed to understand both the physical and electrical influences of the wafer bonding process on electronic devices. The specific objectives of that work were to understand the mechanisms necessary to achieve an electrically benign bonded interface;6 generate sufficient mechanical stability for the fabrication of reliable power devices;7 and determine methods to eliminate voids or bubbles at the bonded interface.8 One of the key technology developments was the creation of NRL's Wafer Bonding Laboratory, which is devoted to the science and technology of wafer bonding.
To achieve the FTO structure shown in Fig. 1, fully fabricated IGBT wafers with only slight modifications were purchased from Dynex Semiconductor. The 100-mm diameter wafers containing 1-cm2 IGBTs rated for 3.3 kV were carefully thinned from the backside and polished by CMP (chemical mechanical polishing). Using NRL's commercial alignment and bond tools, top and bottom IGBTs were joined by direct wafer bonding (the dashed line in the device cross section of Fig. 1 indicates the position of the bonding interface). In the wafer bonding process, the smooth backside silicon surface of the IGBT wafer is treated with a highly dilute hydrofluoric acid solution that removes (etches) the native silicon dioxide and leaves the silicon surface hydrogen-terminated and fully passivated against further oxidation. When the two wafers are carefully joined in clean room conditions, long-range van der Waals bonds between the surface hydrogen atoms pull the wafer surfaces together with sufficient force to maintain the wafers in the aligned and joined position. Annealing the wafers at a low temperature of 400°C for 4 hours significantly increases the strength of the bond by desorbing hydrogen from the interface and forming bridging silicon bonds across the interface. At this point the wafers are ready for "back end" processing, which includes additional metal depositions to improve solder adhesion during the packaging process. The transistor described thus far is fully symmetrical; however, there are also advantages for creating an asymmetrical structure that can block voltage in only one direction but can pass current in both directions. The benefit this structure is faster turn-off, which is achieved by incorporating an additional n-type region, or "buffer layer" on the bottom of the transistor (as shown by the lower n+ layer in Fig.1). The primary effect of the buffer is to reduce the lateral series resistance in the n-base adjacent to the bottom p-region (see Fig. 1). As described below, this has a significant effect on the transistor properties.
Advanced packaging techniques incorporating several novel features were used to improve reliability and reduce parasitic inductance of the module. Figure 4 shows a schematic cross section of the packaged module. The FTO die is soldered to a copper/aluminum nitride/copper substrate. The aluminum nitride is highly insulating to support high anode voltages and also has high thermal conductivity to reduce thermal resistance to the cold plate. The copper on one side of the substrate was patterned to allow connection of the individual gate and emitter contacts on the bottom of the FTO. The perforated alumina/tungsten/nickel ThinPak9 lid, which is also patterned to pick up the emitter and gate pads, is soldered onto the top of the FTO and is then soldered to the external copper lugs. This arrangement eliminates the less reliable wire bonds typical of conventional packages while also reducing the parasitic inductance. Once the transistor and ThinPak lid are mounted, the entire module is hermetically sealed with epoxy. Overall this packaging technology is highly robust. The ThinPak lid also solves the key problem in implementing double-side cooling, which is extremely desirable for high-performance switching transistors.
The key static characteristics for power transistors are the forward voltage drop (and its temperature dependence), the blocking or breakdown voltage, and the leakage current during the blocking condition. Figure 5 shows the blocking voltage characteristics of several wafer-bonded FTOs. Excellent blocking capability is observed up to the design value of 3.6 kV. No degradation in the breakdown voltage or excess leakage current is observed as the electric field penetrates the bond interface, which occurs for voltages of 1200-1400 V. Figure 6 shows the forward current-voltage characteristics for an FTO transistor and is compared to a conventional (single-gate) IGBT. The two operational modes of the FTO are shown: (1) when only the top gate (G1) is conducting, and (2) when both gates are conducting. First, when operating in the conventional mode (G2 OFF), the forward voltage drop of the FTO is approximately 40% lower than the comparable state-of-the-art 3.3 kV IGBT. Second, when the bottom gate is activated (G2 ON) and conductivity modulation is disrupted, the forward drop significantly increases. A sharp increase in current occurs at 50 A; this indicates that conductivity modulation, while delayed, still occurs in the device. The resurgence of conductivity modulation is the result of a voltage drop of approximately 0.7 V across the n-base adjacent to the lower p-region (and shown by the resistor in Fig. 1). The voltage drop allows the p-n junction to become forward biased, leading to strong hole injection into the base. To improve the ability to control hole injection from the lower p-region, transistors with n-buffer layers were fabricated. The n-buffer, which locally increases the conductivity of silicon by approximately 100, acts to decrease the parasitic resistor in the n-base and leads to more ideal transistor characteristics. Figure 7 shows the current-voltage characteristics of an FTO fabricated with a buffer layer. There is a small increase in the forward voltage drop in the conventional mode of operation (G2 OFF) resulting from slightly lower hole injection across the buffer layer. With both gates conducting (G2 ON), however, the current voltage characteristic is linear or purely resistive, indicating that the bottom gate has completely halted hole injection and thus conductivity modulation. With the bottom gate, G2, activated, the device now resembles a unipolar transistor since only one carrier type (electrons) is present. The ability to switch a power transistor between bipolar and unipolar modes of operation is significant: the bipolar mode is required for low voltage drop, and as shown below, the unipolar mode is extremely advantageous for efficient switching operation. Finally, Fig. 8 shows the forward current voltage characteristic at room temperature and 125 °C. The desired behavior is observed: as the temperature increases, the forward voltage drop increases. This prevents any one transistor or portion of a transistor from becoming overheated due to thermal runaway. In high current applications where many transistors are paralleled, it is critical that the forward voltage drop have a positive temperature coefficient for reliable operation.
Transistor turn-off is evaluated by pulsing current from a charged capacitor bank through an inductor to simulate the inductive load of a motor. This transient analysis was carried out on FTOs at currents up 100 A and voltages up to 2400 V. Figure 9 shows a typical turn-off transient characteristic in which the bottom gate of the FTO is always off, and thus the transistor is operating in the conventional mode. At the beginning of the pulse cycle, Gate 1 is on and the transistor is conducting. When the target current is reached, Gate 1 is turned off. At this point, the current ceases and the high voltage is supported across the thick n-base region, which is now mostly depleted of charge carriers. The tail current (red trace) that follows the switching event is due to the slow removal of holes from the n-base and accounts for all of the switching loss (pink trace). It is customary to integrate switching power loss over the switching event to generate a total energy loss value for the given switching conditions. Figure 10 shows similar switching conditions, however with the bottom gate activated 6 μs prior to the turn-off initiated by the top gate. The tail current is completely eliminated, and the total switching loss is reduced by 80%. If the Gate 2 signal is activated too far in advance of deactivating the Gate 1 signal, the forward voltage drop of the transistor begins to increase rapidly. The beginning of this can be seen in Fig. 10, where the voltage trace (blue) begins to rise prior to the switching event due to the transition to a unipolar transistor. Figure 11 shows how this "pre-switch" as well as the tail or "post-switch" energy loss components contribute to the total energy loss. Overall, these results represent better than a factor of three improvement over the fastest devices available today while maintaining greater than 40% lower forward voltage drop.
The development of a new high-voltage power switching transistor that combines off-the-shelf parts and a novel direct wafer bonding process is presented. The development program has led to the demonstration of a device with significantly enhanced performance and efficiency. The transistor has lower forward voltage drop and significantly lower switching loss than high voltage state-of-the-art power transistors. The bidirectional nature of the transistor allows for unique compact circuit topologies that additionally improve performance.
The authors thank Kenneth Brandmier of Silicon Power Corporation, Malvern, PA, for packaging expertise; Peter Waind of Dynex Semiconductor, UK, for process design modifications and helpful discussions.
[Sponsored by ONR]
1 F.J. Kub, V. Temple, K. Hobart, J. Neilson, "Methods for Making Semiconductor Device by Low Temperature Direct Bonding," U.S. Patent #6,194,290, issued February 27, 2001.
2F.J. Kub, V. Temple, K. Hobart, and J. Neilson, "Advanced Methods for Making Semiconductor Devices by Low Temperature Direct Bonding," U.S. Patent #6,153,495, issued November 28, 2000.
3F.J. Kub, V. Temple, K. Hobart, and J. Neilson, "Devices Formable by Low Temperature Direct Bonding," U.S. Patent #6274892, issued August 14, 2001.
4 K.D. Hobart, F.J. Kub, M. Ancona, J.M. Neilson, K. Brandmier, P. Waind "Characterization of a Bi-Directional Double-Side, Double-Gate IGBT Fabricated by Wafer Bonding," Proceedings of the 13th International Symposium on Power Semiconductor Devices and ICs, Osaka, Japan, June 4-8, 2001, pp. 125-128.
5 J.M. Neilson, F.J. Kub, K.D. Hobart, K. Brandmier, and M. Ancona, "Double-Side IGBT Phase Leg Architecture for Reduced Recovery Current and Turn-On Loss," Proceedings of the 14th International Symposium on Power Semiconductor Devices & ICs, 2002, pp. 141-144.
6 F.J. Kub, K. D. Hobart, and C.A. Desmond, "Electrical Characteriza-tion of Low-Temperature Direct Silicon-Silicon Bonding for Power Device Applications," in Semiconductor Wafer Bonding: Science, Technology and Applications IV, edited by U. Goesele, H. Baumgart, T. Abe, C. Hunt, and S. Iyer, Proceedings, Vol. 97-36, The Electrochemical Society, Inc. 1998, pp. 466-472.
7C.A. Desmond, K.D. Hobart, F.J. Kub, G. Campisi, and M. Weldon, " Low Temperature Atmospheric Silicon-Silicon Wafer Bonding for Power Electronics," in Semiconductor Wafer Bonding: Science, Technology and Applications IV, edited by U. Goesele, H. Baumgart, T. Abe, C. Hunt and S. Iyer, Proceedings, Vol. 97-36, The Electrochemical Society, Inc. 1998, pp. 459-465.
8 R.H. Esser, K.D. Hobart, F.J. Kub, "Directional Diffusion and Void Formation at Si(100) Bonded Wafer Interfaces," J. Appl. Phys. 92(4), 2297-2303 (2002).
9 V. Temple, "ThinPak Package for Power Modules and Hybrids," PCIM Europe, November 2000, p. 18.